Technical Field
The present invention relates to an electrical package system; especially relates to a system in package (SiP) without using the following components: discrete solder balls, discrete interposer, discrete package substrate, underfill, and discrete system board.
Description of Related Art
FIG. 1 Shows a Prior Art.
FIG. 1 shows chips 101, 102 configured on a top side of a traditional system in package. Three pluralities of solder balls 141, 142, 143 have been used to join each two components of the system. A first plurality of solder balls 141 join the chips 101, 102 to the silicon interposer 11. A second plurality of solder balls 142 join the silicon interposer 11 to the package substrate 12. A third plurality of solder balls 143 join the package substrate 12 to the system board 13.
Each of the chips 101, 102 has a plurality of I/O pads 103 configured on a bottom side of the chip. The silicon interposer 11 has a core silicon substrate 110. A plurality of conductive through silicon vias (TSVs) 171 passes through the core silicon substrate 110 as an electrical connection between a top redistribution layer (RDL) 111 and a bottom redistribution layer (RDL) 112. The top RDL 111 is configured on a top surface of the silicon substrate 110, and a bottom RDL 112 is configured on a bottom surface of the silicon substrate 110. The plurality of first solder balls 141 are configured between the plurality of I/O pads and the top RDL 111 as an electrical connector there between.
A package substrate 12 is configured on a bottom side of the silicon interposer 11. The package substrate 12 has a core substrate 120 made of laminates and prepregs, a plurality of conductive through laminate vias (TLVs) 172 pass through the core substrate 120. A top RDL 121 is configured on a top side of the core substrate 120, and a bottom RDL 122 is configured on a bottom side of the core substrate 120. A plurality of second solder balls 142 are configured between the silicon interposer 11 and the package substrate 12 as an electrical connector there between. The TLVs 172 electrically couples the top RDL 121 and the bottom RDL 122.
A system board 13 is configured on a bottom of the package substrate 12. The system board 13 has a core substrate 130 made of laminates and prepregs, a plurality of conductive through laminate vias (TLVs) 173 passes through the core substrate 130. A top RDL 131 is configured on a top side of the core substrate 130 and a bottom RDL 132 is configured on a bottom side of the core substrate 130. A plurality of third solder balls 154 are configured between the package substrate 12 and the system board 13 as an electrical connector there between. The TLVs 173 electrically couples the top RDL 131 and the bottom RDL 132.
A first underfill 151 is filled into a space between chips 101, 102 and the silicon interposer 11. A second underfill 152 is filled into a space between silicon interposer 11 and the package substrate 12. A third underfill 153 is filled into a space between the package substrate 12 and the system board 13.
The prior art uses three plurality of solder balls 141, 142, 143 as the electrical connectors to join neighbored two electrical components of the system. The prior art further uses a silicon interposer 11 as an electrical connector between the chips 101, 102 and the package substrate 13. The prior art further uses a discrete system board 13. The prior art further more uses three underfill 151, 152, 153 for advancing the reliability between the interface of the neighbored two discrete electrical components. It is a bulky electronic system. In response to a demand for smaller, lighter and thinner consumer products, a new electronic system meeting the demand has been eager to develop.